The present invention relates to electronic devices, and more specifically to electrostatic discharge (ESD) protection structures for protecting an integrated circuit from ESD damage.
ESD protection has been a main concern in the reliability of integrated circuit (IC) products in submicron complimentary metal-oxide-silicon (CMOS) technologies. For example, drain diffusion regions in N-type metal-oxide-silicon (NMOS) and P-type metal-oxide silicon (PMOS) transistors in output buffers of a CMOS IC are often directly connected to output pads of the IC in order to drive external loads of the IC, causing the CMOS output buffers to be vulnerable to ESD damage. To improve ESD robustness of a CMOS output buffer, the NMOS and PMOS transistors in the output buffer are usually designed with large device dimensions. But the increase in the device dimensions in output buffers is inconsistent with the general trend to reduce device size. Therefore, efforts have been made to design ESD protection structures in the input and output circuitry of an IC that offer sufficient ESD protection while taking up as little area in the IC as possible. In addition, high speed pins of the IC often require low capacitance in the associated circuitry. Therefore, efforts have also been made to design ESD protection structures with low capacitance.
Lateral semiconductor-controlled rectifier (SCR) devices have been widely used in ESD-protection structures for input protection in submicrometer CMOS IC""s. See R. N. Rountree, et al., xe2x80x9cA Process-Tolerant Input Protection Circuit for Advanced CMOS Proceses,xe2x80x9d 1988 EOS/ESD Symposium Proceedings, p. 201. For the output buffers, a low-voltage triggering SCR (LVTSCR) with an inserted NMOS transistor in a lateral SCR structure has been used to provide a much lower trigger voltage than a conventional SCR. The inserted NMOS transistor in the LVTSCR is designed with its gate grounded to provide a low breakdown voltage for the drain-substrate diode at the gate edge. The low breakdown voltage leads to a low trigger voltage for the LVTSCR. Thus the ESD trigger voltage of the LVTSCR device is equivalent to a snap-back trigger voltage of the inserted short-channel NMOS transistor, which is typically much lower than a switching voltage of the original lateral SCR device. See A. Chatterjee, et al., xe2x80x9cA Low-Voltage Triggering SCR for On-chip ESD Protection at Output and Input Pad,xe2x80x9d IEEE Electron Device Letters, Vol. 12, No. 1, January 1991, p. 21. However, the LVTSCR device can have a higher than desirable capacitance due to the usage of the NMOS transistor as the trigger device.
Another SCR structure that offers a low trigger voltage is the triple well SCR device presented by Nikolaidis and Papadas in xe2x80x9cA Novel SCR ESD Protection for Triple Well CMOS Technologies,xe2x80x9d IEEE Electron Device Letters, Vol. 22, No. 4, April 2001, p. 185. This device incorporates a P-well to trigger an RC circuit, and provides a trigger voltage even lower than that of the LVTSCR device. However, the use of the P-well is disadvantageous because it requires more area on the substrate.
The present invention provides a novel ESD structure for protecting an IC from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention meets the requirements of low trigger voltage and low capacitance, and requires less substrate area than prior art ESD structures. The low trigger voltage is provided by a small N+P diode or a P+N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and do not require additional masking steps beyond those already required to fabricate the IC. In one embodiment of the present invention, the lighter doped diffusion region of the N+P or P+N diode can be formed using a lightly doped drain (LDD) implant process for forming LDD diffusion regions in the IC, and the higher doped diffusion region of the NP or P+N diode can be formed using a source/drain implant process for forming source/drain diffusion regions in the IC. The ESD device of the present invention also takes up very little area on a semiconductor substrate because it has a very compact layout and does not require any MOS devices for triggering. The compact layout and the absence of a MOS trigger device also lead to low capacitance for the input or output pads being protected.